`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/02/25 14:36:31
// Design Name: 
// Module Name: flowing_led
// Project Name: 
// Target Devices: 
// Tool Versions:  
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module flowing_led(
    input clk,
    input rst_n,

    output wire [3:0] led

    );
    parameter max_cnt = 8;
    reg [7:0] cnt;
    reg [1:0] state;

    parameter s0=2'b00;
    parameter s1=2'b01;
    parameter s2=2'b10;
    parameter s3=2'b11;

//计数器
    always @(posedge clk or negedge rst_n)
    begin
        if (!rst_n)
        cnt <= 8'b0;
        else if (cnt==max_cnt)
        cnt <= 8'b0;
        else
        cnt<=cnt+1;
    end

//状态跳转
    always @(posedge clk or negedge rst_n)
    begin
        if(!rst_n)
        state<=s0;
        else
        begin
            case(state)
                s0:
                begin
                    if(cnt==max_cnt) //跳转条件
                    state<=s1;
                    else
                    state<=state;
                end
                s1:
                begin
                    if(cnt==max_cnt)
                    state<=s2;
                    else
                    state<=state;
                end
                s2:
                begin
                    if(cnt==max_cnt)
                    state<=s3;
                    else
                    state<=state;
                end
                s3:
                begin
                    if(cnt==max_cnt)
                    state<=s0;
                    else
                    state<=state;
                end
                
                default:
                    state<=s0;
            endcase
        end
    end

//状态输出
assign led=(state==s0)?4'b1000:
            (state==s1)?4'b0100:
            (state==s2)?4'b0010:
            (state==s3)?4'b0001:4'b1000;

endmodule
